1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a manufacturing method thereof.
2. Description of the Related Art
As a nonvolatile semiconductor memory mounted on an electronic device, for example, a NAND- or NOR-type flash memory is extensively used.
In order to improve characteristics of a memory cell transistor constituting the flash memory, elements having various kinds of structures and a manufacturing method of obtaining such elements (see, e.g., JP-A 2006-186073 [KOKAI)) have been proposed, and miniaturization of the memory cell transistor has advanced for a reduction in size and integration in recent years.
However, when miniaturization of the memory cell transistor advances, physical effects which are not a problem in a conventional technology tend to become obvious, which is a factor of degradation in characteristics and a reduction in reliability of the memory cell transistor.
As one of such degradation, there is degradation in characteristics due to a structure of the memory cell transistor at a channel end.
When a floating gate electrode is formed in an active region after an isolation insulating layer is formed in an element isolating region, a gate end of the floating gate electrode in a channel width direction sags toward a semiconductor substrate side. Therefore, this sag causes a parasitic transistor effect at the gate end to become prominent, and kink characteristic occurs due to this effect.
Further, when the floating gate electrode sags, a gate insulating film (a tunnel oxide film) has a structure with a convex shape with respect to the floating gate electrode.
Therefore, an FN tunneling current in a writing/erasing operation is concentrated on the gate end, thereby provoking degradation in the gate insulating film (the tunnel oxide film).
On the other hand, in case of depositing a floating gate material on the gate insulating film (the tunnel oxide film) and then forming the floating gate electrode and an element isolation trench in a self-alignment manner, a side surface of a floating gate in the channel width direction and a side surface of a silicon substrate in a channel section are oxidized by a later-performed oxidizing step, and a dimension of the floating gate electrode in the width direction becomes smaller than a channel width because an oxidizing rate of the silicon substrate is lower than an oxidizing rate of the floating gate electrode consisted of polysilicon.
Therefore, an electric field at the channel end is weakened, and hence a parasitic transistor occurs at the channel end, thus degrading characteristics of the memory cell transistor.
Further, in a manufacturing method of this floating gate electrode, a control gate electrode is configured to cover the side surface of the floating gate electrode through an inter-gate insulating film in order to improve a coupling ratio of the memory cell transistor. Therefore, the control gate electrode is placed closer to the gate insulating film (the tunnel oxide film).
Accordingly, a potential at the control gate electrode affects an electric field at the channel end, thereby degrading characteristics of the memory cell transistor.